Thin film transistors (TFTs) are used extensively in electronic display and detection systems. For example, TFTs are commonly used to rapidly switch individual pixels on and off in large area imaging devices, large area liquid crystal displays, and solid state radiation imagers. In such devices each pixel can be individually addressed through the use of scan and data lines and a TFT associated with each pixel; the scan line is typically coupled to the gate of the TFT to cause it to become conductive or non-conductive while the source/drain electrodes are connected to couple the data line to the pixel when the TFT is conductive.
Each imager array may include many thousands of pixels. It is important for efficient electrical functioning of the array that each TFT switching device operate within known parameters, allowing use of relatively low voltage control signals to switch the devices on and off rapidly with a minimum of associated electronic noise. One important factor affecting imager array performance is the source/drain-to-gate (S/D-G) capacitance of the TFTs in the array. The S/D-G capacitance is determined in large part by the source and drain electrodes overlap of the gate electrode; excessive overlap results in an excessive S/D-G capacitance, while too much spatial separation between the source/drain and gate electrodes can result in high on-resistances and too-high saturation drain currents.
It is desirable to use a self-alignment technique in fabricating a TFT (or more particularly, an array of TFTs) to ensure that the channel gap between the source and the drain electrodes is optimized and is substantially uniform for each TFT in the array. An efficacious TFT self-alignment fabrication technique is disclosed by G. Possin and C. Wei in U.S. Pat. No. 5,010,027, issued Apr. 23, 1991 (the "'027 patent"). This patent is assigned to the assignee of the present invention and is incorporated herein by reference. As is disclosed by the '027 patent, a channel plug made of an insulative material and having selected dimensions is disposed over the gate electrode on the semiconductive layer. The dimensions of the channel plug determine the extent to which the source and drain electrode tips overlap the underlying gate electrode. In the assembled device, the tips of the source and drain electrode extending over the gate electrode are separated from the channel plug by a relatively thin layer of a doped semiconductive material.
Another factor in TFT performance is end leakage of the device. End leakage refers to the undesired current paths remaining along the ends of the channel plug and ends of the underlying semiconductive layers which are not adjacent to the source or drain electrodes. Such current leakage adversely affects array performance in that control currents to turn the TFT on or off may need to be increased. Further, the minimum leakage current may be too large to be employed in some types of arrays. High leakage may reduce the charge or voltage below a minimum operational level on the pixel element during the relatively long time periods between successive connections (via the TFT) of the pixel to the bus line. For example, the TFT is switched to connect the bus line to the pixel to set the voltage in a liquid crystal device or to read the pixel charge in an imaging device.
End leakage in self-aligned TFTs, such as those fabricated in accordance with the method disclosed in the '027 patent, may arise when residual doped semiconductor material adheres to the channel plug end sides (i.e., the sidewalls of the channel plug that extend between the respective tips of the source and drain electrodes) and when a portion of the semiconductive layer sidewalls underlying (or in the vicinity of and substantially aligned with) the channel plug end sides is contaminated with dopant from the doped semiconductive material used in the fabrication process. In both of these situations, the contaminating material that is the source of the end leakage is not readily removed in the normal fabricating steps due to its location along the substantially vertical sidewalls of the channel plug and underlying semiconductive layer.
It is therefore an object of this invention to provide a method of fabricating a TFT that results in reduced end leakage in the fabricated device.
A further object of this invention is to provide a fabrication method that removes portions of the TFT channel plug end sides that had been in contact with the doped semiconductive material during the fabrication process.
Another object of the invention is to provide a fabrication method that removes portions of the semiconductive layer in the vicinity of the channel plug end sides that had been in contact with the doped semiconductive layer.
A yet further object of the invention is to provide a TFT exhibiting relatively low end leakage currents.